1. Field of the Invention
This invention relates generally to treating a dielectric material prior to the electroless deposition of a metal thereon and more particularly relates to an improved three step catalytic seeding method to prepare a dielectric material for the electroless deposition of a conductive metal thereon.
2. Description of the Prior Art
In the manufacture of printed circuit cards, boards and the like, a dielectric sheet material is used as a base upon one or both sides of which a suitable conductive circuit pattern is made. In a preferred method for generating such printed circuit assemblies, the circuitized patterns are generated using a plating process. However, since the dielectric base material is nonconductive, it is first necessary to generate a surface coating, or a predetermined surface pattern, using an electroless deposition technique to provide a thin conductive layer which may be further plated by conventional processes. When both surfaces of the dielectric base material are to be plated, it is also necessary to provide holes through the dielectric to permit the electrical interconnection between the various circuit configurations on the two surfaces.
The art of electroless deposition of conductive materials on dielectric substrates has been highly developed over the years as exemplified by U.S. Pat. Nos. 3,011,920, 3,099,608 and 3,632,388. In U.S. Patent 3,011,920, the method for catalyzing the dielectric substrate includes sensitizing the substrate by first treating it with a solution of a colloidal metal, accelerating the treatment with a selective solvent to remove protective colloids from the sensitized dielectric substrate and then electrolessly depositing a metal coating on the sensitized substrate; for example, with copper from a solution of a copper salt in a reducing agent. U.S. Pat. No. 3,099,608 pretreats a dielectric substrate by depositing a thin film of a "conductivator" type of metal particle such as palladium metal from a semicolloidal solution onto the dielectric substrate to provide a conducting base which permits electroplating with conductive metal on the conductivated base. U.S. Pat. No. 3,632,388 discloses a method for treating a polymeric plastic substrate in a plating process which utilizes a preliminary chromic acid etch followed by a one step activation in a tin-palladium hydrosol.
The foregoing prior art methods have provided satisfactory results for electroless deposition or electroplating thin layers of conductive materials on nonconductive dielectric substrates for most prior art applications. However, with the advent of high circuit densities for printed circuit boards, coupled with reduced line widths and thinner dielectric base materials, the foregoing processes are not totally capable of providing high quality boards with the desired reliability.
With the increased circuit densities have come the requirements that the plated through holes between the sides of the printed circuit boards, or between a number of circuit boards in a multilayer package, have a substantially reduced diameter so that the actual area for plating in the through holes has been significantly decreased. This results in a reduced plating area in the through holes and as a result any deficiency in the seeding or plating process will become more evident.
It has been found that using the prior art seeding techniques, voids can exist in the plated through holes, regardless of how long the board is left in the plating bath. While the exact reason for this is not known, one theory is that the extended exposure of the plated through hole to the plating bath may cause removal of the seeder from the surface of the plated through hole with the result that no adhesion of the electrolessly deposited metal can occur. It has been found that the longer a board must be immersed in an electroless bath before the catalyst is covered with copper, the more likely it is that there is removal of the catalytic seeder from the surfaces of the board. Typically, the electroless deposition take time following prior art seeding processes has been on the order of sixty to ninety minutes.
Another problem that has become evident with the advent of the higher circuit densities, the thinner dielectric materials and the higher aspect ratio of the through holes is the phenomenon of copper wicking. This is due to the absorption of copper into the glass fiber bundles, the absorption of which is directly related to the amount of time that the dielectric is immersed in the electroless deposition bath before initial coverage. With the thinner dielectrics, there has been a substantial increase in the number of internal shorts detected in making circuit boards with the prior art processes. It is therefore apparent that the longer a dielectric must remain in an electroless deposition bath before initial coverage, the more likelihood that increased copper wicking will occur with the resultant evidence of internal shorts through the dielectric.